axel/zynq_can
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4 commits 1 branch 0 tags 120 MiB
  • VHDL 59%
  • C 26.2%
  • Verilog 8.2%
  • SystemVerilog 1.3%
  • Assembly 1.1%
  • Other 4%
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Axel Karch d32b82de2a README.md aktualisiert
2026-04-10 16:10:57 +00:00
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README.md README.md aktualisiert 2026-04-10 16:10:57 +00:00
top_wrapper.xsa initioal checkin 2026-04-10 17:15:56 +02:00
zynq_can.xpr initioal checkin 2026-04-10 17:15:56 +02:00

README.md

zynq_can